Exemplary embodiments of the present invention relate to a semiconductor memory device, and more particularly, to a refresh control circuit and method for a semiconductor memory device.
A memory device, for example, a Dynamic Random Access Memory (DRAM) device, includes a plurality unit cells each of which has one transistor and one capacitor, and data is preliminarily stored in the capacitor. However, since a capacitor formed over a semiconductor substrate is not completely electrically disconnected from its surroundings in a memory device, the data stored in the capacitor may be discharged, and thus, the data may not be retained. In short, leakage current occurs and data of a memory cell may be damaged. To address the problem, the memory device periodically performs a refresh operation to retain the charge which was stored in the capacitor.
A memory device having a refresh operation mode performs a refresh operation while sequentially varying the internal address based on an external command. In other words, when the memory device enters the refresh operation mode based on an external command, a word line of a memory cell is selected as a row address sequentially increases at a predetermined period. The charge stored in the capacitor corresponding to the selected word line is amplified by a sense amplifier and then stored again in the capacitor. Through a series of the refresh process, the stored data is retained without being damaged.
FIG. 1 is a block diagram illustrating a conventional semiconductor memory device for controlling a refresh operation.
As shown in the drawing, the conventional semiconductor memory device 100 for controlling a refresh operation includes a command generator 110, a refresh counter 120, a row address decoder 130, and a cell array 140.
The command generator 110 decodes external commands CSB, RASB, CASB and WEB inputted from the outside of the semiconductor memory device in response to a clock CLK to generate internal commands REF and ACTMD. Herein, the external command “CSB” denotes a chip selection signal, and the external command “RASB” denotes a row address strobe signal. The external command “CASB” denotes a column address strobe signal, and the external command “WEB” denotes a write enable signal. Also, the internal command “REF” denotes a refresh signal, and the internal command “ACTMD” denotes an active mode signal.
The refresh counter 120 counts the refresh signal REF in response to the active mode signal ACTMD outputted from the command generator 110, and outputs a refresh address RA<0:N> so that all the word lines in the cell array 140 are sequentially accessed.
The row address decoder 130 decodes the refresh address RA<0:N> generated in the refresh counter 120 during a refresh operation mode and generates a row address selection signal BX_ADD for selecting a row address to perform a refresh operation.
The cell array 140 retains a stored charge by performing a refresh operation based on the row address selection signal BX_ADD, and thus, prevents data from being lost.
Hereafter, a conventional method for controlling a refresh operation of a semiconductor memory device is described with reference to FIG. 1.
First, the command generator 110 enables the active mode signal ACTMD. Herein, the refresh counter 120 counts the refresh signal REF in response to the active mode signal ACTMD outputted from the command generator 110 and outputs the refresh address RA<0:N>. The row address decoder 130 decodes the refresh address RA<0:N> outputted from the refresh counter 120 and generates the row address selection signal BX_ADD for selecting a row address to perform a refresh operation. Therefore, the cell array 140 retains the stored charge by performing the refresh operation in response to the row address selection signal BX_ADD and prevents the data from being lost. Herein, the refresh operation is performed for one refresh row cycle time tRFC.
The conventional refresh method, however, has a drawback in that it cannot vary the amount of generated noise because it is difficult to change the sequence of refresh addresses. Particularly, since the refresh operation is performed at a period determined based on an average retention time under the assumption that all cells have the same retention time during a test mode, a cell which does not have sufficient retention time loses the data stored therein. This is because, although the cell which does not have sufficient retention time needs to perform the refresh operation at a shorter refresh period than the determined period, the conventional refresh method makes it perform the refresh operation according to the period determined based on the average retention time.